Software-based counters are well known. For example, a counter may be maintained in a dedicated location in main memory of a processor, and incremented upon the occurrence of each event to be counted. However, if events to be counted occur frequently and/or a considerable number of counters are maintained in main memory, the updating of the counters in the main memory may consume an undue proportion of the bandwidth available for accessing the main memory.
To avoid this problem, it is known to provide cached counters, i.e. counters maintained in a processor's on-board memory. However, if the number of counters to be maintained is considerable, then an excessive amount of the limited on-board memory space may be taken up by the counters.
In another known technique, a counter is maintained in main memory and at times the value of that counter is temporarily stored in cache memory and incremented in cache memory in response to events to be counted. After a period of incrementing the counter value in cache memory, the incremented counter value is stored back in main memory. However, the use of cache memory may be excessive during the times that the counter value is cached.
In network processors the need for and use of counters may be sufficiently intensive that prior art counter arrangements are unsatisfactory. For example, it may be necessary to compile extensive statistics that require much counting. The events to be counted may include receipt and/or dispatch of data frames, or bus utilizations (numbers of commands asserted on a bus). It may even be necessary to count individual bytes received or transmitted.
Particularly in view of the counting requirements of network processors, it would be desirable to provide a counter arrangement that neither requires an excessive quantity of the bandwidth available for accessing main memory nor consumes a large part of on-board memory.